Dynamic random access memories (DRAMs) are the most widely used form of semiconductor memory to date. DRAMs are composed of a memory cell array and peripheral circuitry required for external input and output. Each memory cell array is formed of a plurality of memory cells for storing unit memory information. Typical memory cells are formed of a transistor, for opening and closing charge and discharge of the capacitor, and a capacitor, for storing electric charges therein. Of primary concern is maximizing the storage capacitance of each memory cell capacitor. This need is particularly acute in light of the demand for 256 Megabit DRAMs today and higher densities in the future, without increasing the chip space required to form the cell and, preferably, allowing a decrease in the chip space per cell. The importance of high density DRAMs cannot be overstated in today's competitive microelectronics market. Devices are becoming smaller, but they are required to perform many more functions at a faster rate.
One way to achieve greater capacitance per unit area is to roughen the surface of the capacitor plate, increasing the surface area. As can be seen from the following equation, the most important parameters involved in achieving maximum charge, Q, stored on the capacitor are the thickness of the insulator (t.sub.ox), the area of the capacitor (A), and the dielectric constant (.epsilon.). The voltage applied to the gate is V.sub.g. EQU Q=(.epsilon..multidot.A.multidot.V.sub.g)/t.sub.ox
Increasing the capacitor area by forming the storage capacitor in a trench shape etched in the substrate is well known in the art, as well as using a stacked capacitor structure. Cylindrical trench stacked type capacitors feature a major part of the capacitor extending over the gate electrode and field isolating film of the underlying transistor. They are generally comprised of a base portion, a standing wall portion, a capacitor insulating film, and a cell plate. Modifications of trenched capacitors include sloping the standing wall portions of the trench, as shown in U.S. Pat. No. 5,444,013 to Akram et al., in order to further increase the area of the trench. However, yet another way of increasing the capacitance per unit area, as evidenced by the above equation, is to increase the capacitor plate surface area.
While the use of cylindrical trench stacked type capacitors increases the capacitance per unit area, this increase is not enough to meet the demands of today's devices. Further attempts to increase capacitance per unit area utilize roughening the surface of the standing wall portion of the DRAM, which comprises the lower plate electrode. A prior art method for forming a rough bottom plate electrode in a trenched capacitor is shown in FIG. 1. After the substrate 12 is etched, forming a trenched opening 14, the lower plate electrode 16 is formed, having a rough electrode layer 18 formed thereupon. The bottom plate electrode is formed of conductively-doped polysilicon layer 16 and the second, rough layer 18 is formed of hemispherical grain (HSG) polysilicon. Subsequently, a thin, insulating dielectric layer is deposited, and the top electrode is formed over the entire trenched structure. As can be seen from the above equation, this dielectric layer must be as thin as possible to maintain the maximum charge stored on the capacitor. Subsequently etching the structure leaves a capacitor cell formed, comprising the inside surface of the trenched opening.
Park et al. teach roughening a polysilicon capacitor surface in U.S. Pat. No. 5,447,878 by depositing silicon at 550 degrees Celsius, the phase transition point between amorphous silicon and polysilicon. Deposition at this temperature yields HSG polysilicon, with grain diameters of approximately 80 nanometers.
Further methods of roughening the bottom plate electrode include growth of "lattice-mismatched crystalline materials," as described in U.S. Pat. No. 5,384,152 to Chu et al. Such methods comprise forming a layer of roughened germanium over a substrate, formation of a bottom plate electrode over the germanium layer, followed by formation of a dielectric insulating layer over the bottom plate electrode, which replicates underlying surface roughness. The bottom plate electrode and dielectric layer must be of sufficient thinness, to facilitate replicating the underlying surface roughness of the germanium layer.
Other methods utilized to roughen the surface of the bottom plate electrode involve etching. One such method provides a spin on glass (SOG) film on the surface of the bottom plate electrode material, such as that described in "Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMS," Solid State Devices and Materials, 1989, pp. 137-140. The SOG material used contains photoresist materials, which facilitate subsequent photolithographic masking and etching of the bottom plate electrode, creating a rough surface.
U.S. Pat. No. 5,366,917, to Watanabe et al., describes roughening the surface of the bottom plate electrode by selective grain growth of polycrystalline silicon, which comprises the electrode material. Silicon is deposited on a substrate using a low pressure chemical vapor deposition (LPCVD) method. Deposition is carried out at the transition temperature between the crystalline phase and the amorphous phase. The silicon film is doped with either phosphorus, boron, or arsenic. Other embodiments comprise depositing amorphous silicon on a substrate, in a vacuum, or inert gas, ambient. Subsequent annealing in a similar ambient provides a roughened bottom plate electrode. The object of such methods is to increase the size of resulting grains. Conventionally, silicon grain diameters range from about 200 to 1,000 angstroms. Grain sizes resulting from such embodiments described above range from 300 to 1,700 angstroms. By controlling hydrogen content in the silicon film deposition chamber, the size and density of resulting grains can be further controlled. Increased concentrations of hydrogen result in larger grain sizes, and vice versa However, disadvantages of this technique include the fact that native oxides remaining on the surface of the film, and micro-crystallites remaining in the bulk of the amorphous silicon film, crystallize simultaneously with that on the outside surfaces of the film. This is undesirable, due to tendency of grains nucleating in the bulk to "swallow" grains nucleating on the surface. This increases the resulting grain size of the material, resulting in a smoother surface. Smoother surfaces decrease the overall capacitance of a memory cell. However, unless processing atmospheres are strictly controlled, and free of oxidizing species, elimination of native oxides and micro-crystallites in the bulk is near to impossible. Strictly controlling the processing atmosphere adds cost and complexity to the fabrication process.
Amorphous silicon is typically deposited using conventional chemical vapor deposition (CVD) techniques. Polysilicon is inherently composed of uneven sized grains throughout, as evidenced by the large number of convex/concave portions along the layer's edge. Therefore, the surface of the polysilicon layer may be uneven, depending on deposition conditions. Additions of dopants to the polysilicon film, such as arsenic and phosphorus, allow for growing larger silicon grains with diameters of up to between 1,000 angstroms to 10,000 angstroms from amorphous silicon, as described in U.S. Pat. No. 5,480,826 to Sugahara et al. However, it is undesirable to increase grain diameters to such large dimensions because it reduces the number of convex/concave portions of the polysilicon wall, resulting in a smoother surface and a smaller resulting surface area. As devices are decreasing in size, and demanded to perform more functions at a faster rate, it is undesirable to decrease the capacitor surface area because it decreases the amount of memory cell capacitance per unit area
Other methods of obtaining surface roughness include roughening by oxidation as taught by Fazan et al. in U.S. Pat. No. 5,043,780 and Chan et al. In U.S. Pat. No. 5,082,797, or through an anodic process as taught by Sandu in U.S. Pat. No. 5,068,199. Both methods are imprecise and add process complexity to the fabrication process.
U.S. Pat. No. 5,384,152 to Chu et al. teaches heteroepitaxial deposition of germanium on the capacitor bottom electrode plate to increase the surface roughness. Chu et al. further report that the growth of any lattice-mismatched crystalline material, such as gallium arsenide or metal suicides, forms "islands," which give the surface its rough texture. Thereafter, a thin conductive polysilicon layer (approximately 500 angstroms thick) is deposited, replicating the rough surface structure of the underlying material. This method adds to process complexity due to the heteroepitaxial deposition step.
U.S. Pat. No. 5,466,626 to Armacost et al. teaches the use of ion sputtering to achieve surface roughness on capacitor surfaces, resulting in greater storage capacity. Armacost et al. achieves this through the use of an agglomerated material mask to selectively etch the surface, leaving recesses in the exposed surface areas. Drawbacks of this technique include the inability to provide a stable contact between the roughened surface and adjacent layers, such as the capacitor insulating film. This problem arises due to the sharp comers in the recesses which arise as a result of the etching process. Furthermore, uniformity of roughness is hard to control using this technique.
While all of the above methods create a roughened surface on the capacitor electrode plate to increase capacitance per unit area, they comprise complicated process steps. There is a need for a method of providing a rough capacitor plate surface using conventional processes, without expensive, time-consuming process steps. There is also a need to provide uniform surface roughness on a capacitor plate for a uniform capacitance effect along the plate. With the rapid decrease in device size, coupled with the demand for increased performance, a new, efficient technique must be used to further increase the capacitance per unit area in DRAM memory cells.